1. Field of the Invention
The present invention relates to the field of memory devices; more particularly, the present invention relates to a method and apparatus for performing bit cell ground choking to improve static random access memory (SRAM) write margin.
2. Description of Related Art
Static random access memory (SRAM) cells are designed to reliably retain their value during a read operation by having an acceptable read stability margin and to reliably modify their value during a write operation by having acceptable write margin.
FIG. 1 illustrates read stability margin in a prior art SRAM cell. An SRAM cell has a bit (B) node and bit bar (B#) node. Whether the value of the bit stored is a logic 1 or a logic 0, one of these nodes will be storing a logic 0. Read stability is typically more critical on the node that stores a logic 0. The following illustration is the case where the bit stored is a logic 0. In that case, the bit node is a logic 0 and the bit bar node is a logic 1. However, similar analysis applies to the bit bar node when the bit stored is a logic 1.
During a read operation, the bit line (BL) column and bit line bar (BL#) column are initialized to a logic 1. The word line (WL) bus is asserted to turn on a transfer gate (transistor T.sub.x) such that the BL column begins to be discharged through a first pull down device (transistor T.sub.pd). While the BL column is being discharged, the voltage at the bit node is determined by the ratio of the resistance of transistor T.sub.X and the resistance of transistor T.sub.pd. The bit node is also the input to the second pull down device (transistor T.sub.trip) which begins to turn on at a voltage V.sub.trip. If the voltage at the bit node exceeds V.sub.trip, the voltage at the bit bar node is pulled down thereby corrupting the data within the SRAM cell by flipping the value of the bit stored.
In order to improve read stability margin, the voltage at the node storing the logic 0 should be reduced and/or the V.sub.trip voltage should be increased. In order to lower the voltage of the bit node, the resistance of transistor T.sub.pd should be made small with respect to the resistance of transistor T.sub.x. In order to increase the V.sub.trip voltage, the resistance of a transistor T.sub.p should be made small with respect to the resistance of transistor T.sub.trip.
FIG. 2 illustrates write margin in a prior art SRAM cell. Write margin, unlike read stability margin, is typically more critical on the node that stores a logic 1. The following illustration is the case where the bit stored is a logic 1 and a write logic 0 operation is being performed. In that case, the bit node is initially a logic 1 and the bit bar node is initially a logic 0. However, similar analysis applies to the bit bar node when the bit stored is a logic 0 and a write logic 1 operation is being performed.
During a write logic 0 operation, the bit line (BL) column is driven to a logic 0 and bit line bar (BL#) column is driven to a logic 1. The word line (WL) bus is asserted to turn on a transfer gate (transistor T.sub.x) such that the voltage at the bit node is determined by the ratio of the resistance of transistor T.sub.x and the resistance a first pull up device (transistor T.sub.pu). The bit node is also the input to the second pull down device (transistor T.sub.trip) which turns off when the voltage of the bit node is below voltage V.sub.trip. In order to successfully write the logic 0, the voltage at the bit bar node must be pulled down below voltage V.sub.trip. This can be difficult because the non-linear resistance of transistor T.sub.x typically increases as the voltage drop across it decreases.
In order to improve write margin, the voltage at the node storing the logic 1 should be pulled lower and/or the V.sub.trip voltage should be higher. As in the case to improve read stability, the resistance of transistor T.sub.p should be made small with respect to the resistance transistor T.sub.trip in order to increase the V.sub.trip voltage. However, unlike the case to improve read stability, the resistance of transistor T.sub.p should be made large with respect to the resistance of transistor T.sub.x in order to lower the voltage drop across transistor T.sub.x.
In order to improve speed, the resistance of transistors T.sub.pd, T.sub.trip, and T.sub.x should be minimized. If one assumes that the resistance of T.sub.x is minimized for speed, read stability considerations suggest reducing the resistance of transistors T.sub.pd, T.sub.pu, and T.sub.trip, whereas write margin considerations suggest increasing the resistance of these transistors. Therefore, the designer must select these parameters within these competing constraints to have acceptable read stability and write margins.
The design window defined by these competing constraints is becoming smaller in each subsequent generation of process technology. Since manufacturing process variability tends to increase relative to the shrinking transistor feature sizes in each generation, it is becoming more difficult to design an SRAM cell that has acceptable margin within the shrinking design window. This problem is exacerbated because not only is there a tendency for the SRAM cell error rate to increase because of the shrinking design window, but the number of SRAM cells per device is increasing.
Power supply voltages are being reduced to reduce power consumption and avoid reliability problems as the transistor feature sizes shrink. The V.sub.trip voltage in a typical SRAM cell is being reduced to track the reduced power supply voltages. However, process variability associated with the V.sub.trip voltage variations do not scale with the V.sub.trip voltage. Therefore the relative variation of the V.sub.trip voltage tends to increase as the transistor feature sizes shrink.
In order to extend the design window, some designs have resorted to driving the word line above the power supply voltage during write operations and driving the word line to the power supply voltage during read operations. This has the effect of reducing the resistance of T.sub.x during write operations as compared with the resistance of T.sub.x during read operations. Therefore, the resistance of T.sub.x is controlled to improve margin for each of these operations thereby widening the design window.
Alternatively, some designs have driven one of the bit lines below ground during write operations. Referring to FIG. 2, the bit node is at a voltage between the power supply voltage and the bit line voltage as determined by the ratio of the resistance of transistor T.sub.pu and the resistance of transistor T.sub.x according to well-known methods. The voltage at the bit node will tend to decrease as the voltage at the bit line decreases. Since the voltage at the bit node is decreased relative to V.sub.trip, write margin is improved without affecting the read margin parameters.
One problem with both these methods is that they require voltages to be driven either above the power supply voltage or below ground. Generating additional voltages adds complexity and cost to a design. In addition, application of voltages beyond the standard power supply range may lead to reliability problems.
What is needed is a method and apparatus to increase the size of the design window for SRAM cells without requiring a voltage above the power supply voltage or below ground.